Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 discloses a split gate non-volatile memory cell, which is incorporated herein by reference for all purposes. FIG. 1 illustrates an example of such a split gate memory cell formed on a semiconductor substrate 12. Source and drain regions 16 and 14 are formed as diffusion regions in substrate 12, and define a channel region 18 therebetween. The memory cell includes four conductive gates: a floating gate 22 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 16, a control gate 26 disposed over and insulated from the floating gate 22, an erase gate 24 disposed over and insulated from the source region 16, and a select gate 20 disposed over and insulated from a second portion of the channel region 18. A conductive contact 10 can be formed to electrically connect to the drain region 14.
The memory cells are arranged in an array, with columns of such memory cells separated by columns of isolation regions. Isolation regions are portions of the substrate in which insulation material is formed. A well-known isolation region forming technique is STI, which involves forming trenches into the surface of the substrate, and filling the trenches with insulation material (e.g. silicon dioxide-oxide). The STI insulation material 28 has an upper surface that is typically even with or slightly higher than the surface of the substrate 12. FIG. 2 illustrates the conventional arrangement of the memory cells and the isolation regions 28. The select gates 20 for an entire row of memory cells are formed as a single conductive line (commonly referred to as a word line) that extends across the columns of STI insulation material 28. The control gates 26 are similarly formed as a continuous control gate line extending along the row of memory cells, as is the erase gate 24.
As device geometries continue to shrink, it is becoming more difficult to operate the memory cell array at lower voltages. For example, lowering the read voltage (e.g. positive voltage on the drain 14) results in a lower read cell current (in the channel region 18), and lowering the select gate voltage results in a higher sub-threshold leakage. Raising the select gate voltage to suppress leakage would result in suppressing the read cell current. There is a need to improve cell current during a read operation without compromising sub-threshold leakage.